Integrating formal results with simulation in the verification plan
Formal verification is a very powerful addition to any chip project, providing proofs and a degree of completeness that simulation cannot match. While formal verification may reduce the amount of simulation needed, it cannot displace simulation entirely. Some aspects of design behavior, including hardware-software co-verification, require simulation or emulation.
Given the modern chip projects rely on a mix of simulation and formal, the verification team needs to be able to plan for using both approaches and to assess the impact of their work in a common top-level views of verification progress. The OneSpin PortableCoverage platform provides these capabilities.
The Verification Planning Integration App adds the results from formal verification with OneSpin’s tools into the verification plan. Engineers can write the verification plan with formal as well as simulation in mind, choosing which features to verify with which techniques, and then annotate the results back into the plan. The plan then shows the integrated results from formal analysis and simulation tests, providing a comprehensive view of verification progress.
Unlike closed, single-vendor ABV flows, OneSpin’s Verification Planning Integration App is open and supports planning tools and simulators from all major vendors.